/* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ /* Modified 06/07/76 by Greenberg for mc.resignal */ /* Modified 07/07/76 by Morris for fault register data */ /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ /* Modified '82 to make values constant */ /* words 0-15 pointer registers */ dcl mcp ptr; dcl 1 mc based (mcp) aligned, 2 prs (0:7) ptr, /* POINTER REGISTERS */ (2 regs, /* registers */ 3 x (0:7) bit (18), /* index registers */ 3 a bit (36), /* accumulator */ 3 q bit (36), /* q-register */ 3 e bit (8), /* exponent */ 3 pad1 bit (28), 3 t bit (27), /* timer register */ 3 pad2 bit (6), 3 ralr bit (3), /* ring alarm register */ 2 scu (0:7) bit (36), 2 mask bit (72), /* mem controller mask at time of fault */ 2 ips_temp bit (36), /* Temporary storage for IPS info */ 2 errcode fixed bin (35), /* fault handler's error code */ 2 fim_temp, 3 unique_index bit (18) unal, /* unique index for restarting faults */ 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 2 fault_reg bit (36), /* fault register */ 2 pad2 bit (1), 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 2 fault_time bit (54), /* time of fault */ 2 eis_info (0:7) bit (36)) unaligned; dcl (apx fixed bin init (0), abx fixed bin init (1), bpx fixed bin init (2), bbx fixed bin init (3), lpx fixed bin init (4), lbx fixed bin init (5), spx fixed bin init (6), sbx fixed bin init (7)) internal static options (constant); dcl scup ptr; dcl 1 scu based (scup) aligned, /* SCU DATA */ /* WORD (0) */ (2 ppr, /* PROCEDURE POINTER REGISTER */ 3 prr bit (3), /* procedure ring register */ 3 psr bit (15), /* procedure segment register */ 3 p bit (1), /* procedure privileged bit */ 2 apu, /* APPENDING UNIT STATUS */ 3 xsf bit (1), /* ext seg flag - IT modification */ 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 3 dsptw bit (1), /* Fetch of DSPTW */ 3 sdwnp bit (1), /* Fetch of SDW non paged */ 3 sdwp bit (1), /* Fetch of SDW paged */ 3 ptw bit (1), /* Fetch of PTW */ 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 3 fap bit (1), /* Fetch of final address paged */ 3 fanp bit (1), /* Fetch of final address non-paged */ 3 fabs bit (1), /* Fetch of final address absolute */ 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ /* WORD (1) */ 2 fd, /* FAULT DATA */ 3 iro bit (1), /* illegal ring order */ 3 oeb bit (1), /* out of execute bracket */ 3 e_off bit (1), /* no execute */ 3 orb bit (1), /* out of read bracket */ 3 r_off bit (1), /* no read */ 3 owb bit (1), /* out of write bracket */ 3 w_off bit (1), /* no write */ 3 no_ga bit (1), /* not a gate */ 3 ocb bit (1), /* out of call bracket */ 3 ocall bit (1), /* outward call */ 3 boc bit (1), /* bad outward call */ 3 inret bit (1), /* inward return */ 3 crt bit (1), /* cross ring transfer */ 3 ralr bit (1), /* ring alarm register */ 3 am_er bit (1), /* associative memory fault */ 3 oosb bit (1), /* out of segment bounds */ 3 paru bit (1), /* processor parity upper */ 3 parl bit (1), /* processor parity lower */ 3 onc_1 bit (1), /* op not complete type 1 */ 3 onc_2 bit (1), /* op not complete type 2 */ 2 port_stat, /* PORT STATUS */ 3 ial bit (4), /* illegal action lines */ 3 iac bit (3), /* illegal action channel */ 3 con_chan bit (3), /* connect channel */ 2 fi_num bit (5), /* (fault/interrupt) number */ 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ /* WORD (2) */ 2 tpr, /* TEMPORARY POINTER REGISTER */ 3 trr bit (3), /* temporary ring register */ 3 tsr bit (15), /* temporary segment register */ 2 pad2 bit (9), 2 cpu_no bit (3), /* CPU number */ 2 delta bit (6), /* tally modification DELTA */ /* WORD (3) */ 2 word3 bit (18), 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 3 tsna, /* Word 1 status */ 4 prn bit (3), /* Word 1 PR number */ 4 prv bit (1), /* Word 1 PR valid bit */ 3 tsnb, /* Word 2 status */ 4 prn bit (3), /* Word 2 PR number */ 4 prv bit (1), /* Word 2 PR valid bit */ 3 tsnc, /* Word 3 status */ 4 prn bit (3), /* Word 3 PR number */ 4 prv bit (1), /* Word 3 PR valid bit */ 2 tpr_tbr bit (6), /* TPR.TBR field */ /* WORD (4) */ 2 ilc bit (18), /* INSTRUCTION COUNTER */ 2 ir, /* INDICATOR REGISTERS */ 3 zero bit (1), /* zero indicator */ 3 neg bit (1), /* negative indicator */ 3 carry bit (1), /* carryry indicator */ 3 ovfl bit (1), /* overflow indicator */ 3 eovf bit (1), /* eponent overflow */ 3 eufl bit (1), /* exponent underflow */ 3 oflm bit (1), /* overflow mask */ 3 tro bit (1), /* tally runout */ 3 par bit (1), /* parity error */ 3 parm bit (1), /* parity mask */ 3 bm bit (1), /* ^bar mode */ 3 tru bit (1), /* truncation mode */ 3 mif bit (1), /* multi-word instruction mode */ 3 abs bit (1), /* absolute mode */ 3 hex bit (1), /* hexadecimal exponent mode */ 3 pad bit (3), /* WORD (5) */ 2 ca bit (18), /* COMPUTED ADDRESS */ 2 cu, /* CONTROL UNIT STATUS */ 3 rf bit (1), /* on first cycle of repeat instr */ 3 rpt bit (1), /* repeat instruction */ 3 rd bit (1), /* repeat double instruction */ 3 rl bit (1), /* repeat link instruciton */ 3 pot bit (1), /* IT modification */ 3 pon bit (1), /* return type instruction */ 3 xde bit (1), /* XDE from Even location */ 3 xdo bit (1), /* XDE from Odd location */ 3 poa bit (1), /* operation preparation */ 3 rfi bit (1), /* tells CPU to refetch instruction */ 3 its bit (1), /* ITS modification */ 3 if bit (1), /* fault occured during instruction fetch */ 2 cpu_tag bit (6)) unaligned, /* computed tag field */ /* WORDS (6,7) */ 2 even_inst bit (36), /* even instruction of faulting pair */ 2 odd_inst bit (36); /* odd instruction of faulting pair */ /* ALTERNATE SCU DECLARATION */ dcl 1 scux based (scup) aligned, (2 pad0 bit (36), 2 fd, /* GROUP II FAULT DATA */ 3 isn bit (1), /* illegal segment number */ 3 ioc bit (1), /* illegal op code */ 3 ia_am bit (1), /* illegal address - modifier */ 3 isp bit (1), /* illegal slave procedure */ 3 ipr bit (1), /* illegal procedure */ 3 nea bit (1), /* non existent address */ 3 oobb bit (1), /* out of bounds */ 3 pad bit (29), 2 pad2 bit (36), 2 pad3a bit (18), 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 3 prn bit (3), /* PR number */ 3 prv bit (1), /* PR valid bit */ 2 pad3b bit (6)) unaligned, 2 pad45 (0:1) bit (36), 2 instr (0:1) bit (36); /* Instruction ARRAY */ /* END INCLUDE FILE mc.incl.pl1 */ /* ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */