Multics > History > Features
14 Oct 2000

DPS 8M Machine Instructions

(This page has a few highlights of chapter 4 of AL39-01, the processor manual for Multics).

Instruction Repertoire

Basic Operations

The 456 basic operations in the processor all require exactly one 36-bit machine word. They are categorized as follows:

181 Fixed-point binary arithmetic
85 Boolean operations
34 Floating-point binary arithmetic
36 Transfer of control
75 Pointer Register
17 Miscellaneous
28 Privileged

Extended Instruction Set (EIS) Operations

The 91 extended instruction set (EIS) operations are divided into 62 EIS single-word instructions and 29 EIS multiword instructions.

EIS Single-word Operations

The 62 EIS single-word instructions load, store, and perform special arithmetic on the address registers (ARn) used to access bit- and character-string operands, and safe-store decimal unit (DU) control information required to service a processor fault or interrupt. Like the basic operations, EIS single-word instructions require exactly one 36-bit machine word.

EIS Multiword Operations

The 29 EIS multiword instructions perform decimal arithmetic and bit- and character-string operations. They require three or four 36-bit machine words depending on individual operand descriptor requirements.

Instruction Word Formats

Basic and EIS Single-Word Instructions

Bits 0-17 - ADDRESS (many formats possible for the address)
Bits 18-27 - OPCODE
Bit 28 - I (Interrupt Inhibit)
Bit 29 - A (Indirect via pointer register flag)
Bits 30-35 - TAG (Instruction address modifier)

Indirect Words

Certain of the basic EIS single-word instructions permit indirection to be specified as part of address modification. When such indirection is specified, C(Y) (the resulting target address of the instruction - Ed.) is interpreted as an indirect word according to the following format:

Bits 0-17 - ADDRESS (many formats possible)
Bits 18-29 - TALLY (count field)
Bits 30-35 - TAG (several formats, depending on TAG of original instruction)

Fixed Point Arithmetic Instructions

Fixed-Point Data Movement Load

eaaEffective Address to A
eaqEffective Address to Q
eaxnEffective Address to Index Register n
lcaLoad Complement A
lcaqLoad Complement AQ
lcqLoad Complement Q
lcxnLoad Complement Index Register n
ldaLoad A
ldacLoad A and Clear
ldaqLoad AQ
ldiLoad Indicator
ldqLoad Q
ldqcLoad Q and Clear
ldxnLoad Index Register n
lregLoad Registers
lxlnLoad Index Register n from Lower
sregStore Registers
stbaStore Bytes of A
stbqStore Bytes of Q
stc1Store Instruction Counter Plus 1
stc2Store Instruction Counter Plus 2
stcaStore Characters of A
stcqStore Characters of Q
stcdStore Control Double
stiStore Indicator Register
stqStore Q
sttStore Time Register
stxnStore Index Register n
stzStore Zero
sxlnStore Index Register n in Lower

Fixed-Point Data Movement Shift

alrA Left Rotate
alsA Left Shift
arlA Right Logical
arsA Right Shift
llrLong Left Rotate
llsLong Left Shift
lrlLong Right Logical
lrsLong Right Shift
qlrQ Left Rotate
qlsQ Left Shift
qrlQ Right Logical
qrsQ Right Shift

Fixed-Point Addition

adaAdd to A
adaqAdd to AQ
adlAdd Low o AQ
adlaAdd Logical to A
adlaqAdd Logical to AQ
adlqAdd Logical to Q
adlxnAdd Logical to Index Register n
adqAdd to Q
adxnAdd to Index Register n
aosAdd One to Storage
asaAdd Stored to A
asqAdd Stored to Q
asxnAdd Stored to Index Register n
awcaAdd with Carry to A
awcqAdd with Carry to Q

Fixed-Point Subtraction

sbaSubtract from A
sbaqSubtract from AQ
sblaSubtract Logical from A
sblaqSubtract Logical from AQ
sblqSubtract Logical from Q
sblxnSubtract Logical from Index Register n
sbqSubtract from Q
sbxnSubtract from Index Register n
ssaSubtract Stored from A
ssqSubtract Stored from Q
ssxnSubtract Stored from Index Register n
swcaSubtract with Carry from A
swcqSubtract with Carry from Q

Fixed-Point Multiplication

mpfMultiply Fraction
mpyMultiply Integer

Fixed-Point Division

divDivide Integer
dvfDivide Fraction

Fixed-Point Negate

negNegate A
neglNegate Long

Fixed-Point Comparison

cmgCompare Magnitude
cmkCompare Masked
cmpaCompare with A
cmpaqCompare with AQ
cmpqCompare with Q
cmpxnCompare with Index Register n
cwlCompare with Limits

Fixed-Point Miscellaneous

sznSet Zero and Negative Indicators
szncSet Zero and Negative Indicators and Clear

Boolean Operations Instructions

Boolean And

anaAND to A
anaqAND to AQ
anqAND to Q
ansaAND to Storage A
ansqAND to Storage Q
ansxnAND to Storage Index Register n
anxnAND to Index Register n

Boolean Or

oraOR to A
oraqOR to AQ
orqOR to Q
orsaOR to Storage A
orsqOR to Storage Q
orsxnOR to Storage Index Register n
orxnOR to Index Register n

Boolean Exclusive Or

ersaEXCLUSIVE OR to Storage A
ersqEXCLUSIVE OR to Storage Q
ersxnEXCLUSIVE OR to Storage Index Register n
erxnEXCLUSIVE OR to Index Register n

Boolean Comparative And

canaComparative AND with A
canaqComparative AND with AQ
canqComparative AND with Q
canxnComparative AND with Index Register n

Boolean Comparative Not

cnaaComparative NOT with A
cnaaqComparative NOT with AQ
cnaqComparative NOT with Q
cnaxnComparative NOT with Index Register n

Floating-Point Arithmetic Instructions

Floating-Point Data Movement Load

dfldDouble-Precision Floating Load
fldFloating Load
dfstDouble-Precision Floating Store
dfstrDouble-Precision Floating Store Rounded
fstFloating Store
fstrFloating Store Rounded

Floating-Point Addition

dfadDouble-Precision Floating Add
dufaDouble-Precision Unnormalized Floating Add
fadFloating Add
ufaUnnormalized Floating Add

Floating-Point Subtraction

dfsbDouble-Precision Floating Subtraction
dufsDouble-Precision Unnormalized Floating Subtraction
fsbFloating Subtraction
ufsUnnormalized Floating Subtraction

Floating-Point Multiplication

dfmpDouble-Precision Floating Multiply
dufmDouble-Precision Unnormalized Floating Multiply
fmpFloating Multiply
ufmUnnormalized Floating Multiply

Floating-Point Division

dfdiDouble-Precision Floating Divide Inverted
dfdvDouble-Precision Floating Divide
fdiFloating Divide Inverted
fdvFloating Divide

Floating-Point Negate

fnegFloating Negate

Floating-Point Normalize

fnoFloating Normalize

Floating-Point Round

dfrdDouble-Precision Floating Round
frdFloating Round

Floating-Point Compare

dfcmgDouble-Precision Floating Compare Magnitude
dfcmpDouble-Precision Floating Compare
fcmgFloating Compare Magnitude
fcmpFloating Compare

Floating-Point Miscellaneous

adeAdd to Exponent
fsznFloating Set Zero and Negative Indicators
ldeLoad Exponent
steStore Exponent

Transfer Instructions

call6Call (using PR6 and PR7)
rtcdReturn Control Double
teoTransfer on Exponent Overflow
teuTransfer on Exponent Underflow
tmiTransfer on Minus
tmozTransfer on Minus or Zero
tncTransfer on No Carry
tnzTransfer on Nonzero
tovTransfer on Overflow
tplTransfer on Plus
tpnzTransfer on Plus and Nonzero
traTransfer Unconditionally
trcTransfer on Carry
trtfTransfer on Truncation Indicator OFF
trtnTransfer on Truncation Indicator ON
tspnTransfer and Set Pointer Register n
tssTransfer and Set Slave
tsxnTransfer and Set Index Register n
ttfTransfer on Tally Runout Indicator OFF
ttnTransfer on Tally Runout Indicator ON
tzeTransfer on Zero

Pointer Register Instructions

Pointer Register Data Movement Load

easpnEffective Address to Segment Number of Pointer Register n
epbpnEffective Pointer at Base to Pointer Register n
eppnEffective pointer to Pointer Register n
lpriLoad Pointer Registers from ITS Pairs
lprpnLoad Pointer Register n Packed
spbpnStore Segment Base Pointer of Pointer Register n
spriStore Pointer Registers as ITS Pairs
sprinStore Pointer Register n as ITS Pairs
sprpnStore Pointer Register n Packed

Pointer Register Address Arithmetic

adwpnAdd Word Number of Pointer Register n

Pointer Register Miscellaneous

epaqEffective Pointer to AQ

Miscellaneous Instructions

Calendar Clock

rcclRead Calendar Clock




xedExecute Double

Master Mode Entry

mmeMaster Mode Entry
mme2Master Mode Entry 2
mme3Master Mode Entry 3
mme4Master Mode Entry 4

No Operation

nopNo Operation
puls1Pulse One
puls2Pulse Two


rpdRepeat Double
rplRepeat Link

Ring Alarm Register

sraStore Ring Alarm Register

Store Base Address Register

sbarStore Base Address Register


bcdBinary to Binary-Coded-Decimal
gtbGray to Binary

Register Load

lbarLoad Base Address Register

Privileged Instructions

Privileged - Register Load

lcprLoad Central Processor Register
ldbrLoad Descriptor Segment Base Register
ldtLoad Timer Register
lptpLoad Page Table Pointers
lptrLoad Page Table Registers
lraLoad Ring Alarm Register
lsdpLoad Segment Descriptor Pointers
lsdrLoad Segment Descriptor Registers
rcuRestore Control Unit

Privileged - Register Store

scprStore Central Processor Register
scuStore Control Unit
sdbrStore Descriptor Segment Base Register
sptpStore Page Table Pointers
sptrStore Page Table Registers
ssdpStore Segment Descriptor Pointers
ssdrStore Segment Descriptor Registers

Privileged - Clear Associative Memory

campClear Associative Memory Pages
camsClear Associative Memory Segments

Privileged - Configuration and Status

rmcmRead Memory Controller Mask Register
rscrRead System Controller Register
rswRead Switches

Privileged - System Control

ciocConnect I/O Channel
smcmSet Memory Controller Mask Register
smicSet Memory Controller Interrupt Cells
sscrSet System Controller Register

Privileged - Miscellaneous

absaAbsolute Address to A-Register
disDelay Until Interrupt Signal

Extended Instruction Set (EIS)

EIS - Address Register Load

asrnAlphanumeric Descriptor to Address Register n
larnLoad Address Register n
laregLoad Address Registers
lplLoad Pointers and Lengths
narnNumeric Descriptor to Address Register n

EIS - Register Store

aranAddress Register n to Alphanumeric Descriptor
arnnAddress Register n to Numeric Descriptor
sarnStore Address Register n
saregStore Address Registers
splStore Pointers and Lengths

EIS - Address Register Special Arithmetic

a4bdAdd 4-bit Displacement to Address Register
a6bdAdd 6-bit Displacement to Address Register
a9bdAdd 9-bit Displacement to Address Register
abdAdd Bid Displacement to Address Register
awdAdd Word Displacement to Address Register
s4bdSubtract 4-bit Displacement from Address Register
s6bdSubtract 6-bit Displacement from Address Register
s9bdSubtract 9-bit Displacement from Address Register
sbdSubtract bit Displacement from Address Register
swdSubtract Word Displacement from Address Register

EIS - Alphanumeric Compare

cmpcCompare Alphanumeric Character Strings
scdScan Characters Double
scdrScan Characters Double in Reverse
scmScan with Mask
scmrScan with Mask in Reverse
tctTest Character and Translate
tctrTest Character and Translate in Reverse

EIS - Alphanumeric Move

mlrMove Alphanumeric Left to Right
mrlMove Alphanumeric Right to Left
mveMove Alphanumeric Edited
mvtMove Alphanumeric with Translation

EIS - Numeric Compare

cpmnCompare Numeric

EIS - Numeric Move

mvnMove Numeric
mvneMove Numeric Edited

EIS - Bit String Combine

cslCombine Bit Strings Left
csrCombine Bit Strings Right

EIS - Bit String Compare

cmpbCompare Bit Strings

EIS - Bit Strings Set Indicators

sztlSet Zero and Truncation Indictors with Bit Strings Left
sztrSet Zero and Truncation Indictors with Bit Strings Right

EIS - Data Conversion

btdBinary to Decimal Convert
dtbDecimal to Binary Convert

EIS - Decimal Addition

ad2dAdd Using Two Decimal Operands
ad3dAdd Using Three Decimal Operands

EIS - Decimal Subtraction

sb2dSubtract Using Two Decimal Operands
sb3dSubtract Using Three Decimal Operands

EIS - Decimal Multiplication

mp2dMultiply Using Two Decimal Operands
mp3dMultiply Using Three Decimal Operands

EIS - Decimal Division

dv2dDivide Using Two Decimal Operands
dv3dDivide Using Three Decimal Operands

Micro Operations for Edit Instructions

(In the mve and mvne instructions, you can 'program' the instruction with a number of operations. Here are their titles. They are not operations, they are sub-operations of mve and mvne)

Micro Operations

chtChange Table (21)
enfEnd Floating Suppression (02)
ignIgnore Source Character (14)
insaInsert Asterisk on Suppression (11) (useful for printing checks from COBOLEd.)
insbInsert Blank on Suppression (10)
insmInsert Table Entry One Multiple (01)
insnInsert On Negative (12)
inspInsert On Positive (13)
lteLoad Table Entry (20)
mflcMove with Floating Currency Symbol Insertion (07)
mflsMove with Floating Sign Insertion (06)
morsMove and OR Sign (17)
msesMove and Set Sign (16)
mvcMove Source Characters (15)
mvzaMove with Zero Suppression and Asterisk Replacement (05)
mvzbMove with Zero Suppression and Blank Replacement (04)
sesSet End Suppression (03)

Last modified: 10/14/00 by Ron Harvey